June 15, 2007 --- NEC Corporation and NEC Electronics Corporation have jointly developed a new breakthrough yield-evaluation method, which enables robust design of low-power, high performance system LSIs. Intrinsic fluctuations*1 in transistors are currently considered to be a major obstacle to stable LSI circuit functionality in the future. The newly developed method enables high yields to be maintained from the early stages of mass fabrication of system LSIs by practical evaluation of the intrinsic fluctuations in device performance by precise, three-dimensional technology-computer-aided design (TCAD) modeling.

The new technology was enabled by the following advancements:

• Analysis of the performance fluctuations of deeply-scaled transistors with accurate three-dimensional atomistic process/device simulation*2 and precise measurement of the microscopic roughness of the critical geometry of the device, enable prediction of device characteristic fluctuations for specific fabrication processes.
  
  
• Conversion of the device characteristic fluctuations into a compact statistical model*3 for very large-scale circuit simulation enables efficient statistical circuit simulation for calculation of design windows and evaluation of areas where productivity can be improved through ease of manufacturing, while maintaining circuit speed and functionality.

Although silicon devices have been achieving higher performance and larger-scale integration through scaling of dimension size in recent years, it is commonly known that variations within individual transistors will increase along with scaling and that random fluctuations will make correct operation of even simple circuits more difficult. Therefore, circuit designers need to consider how to optimize design margins much more carefully in order to maintain circuit functionality in the future. However, appropriate margins are unknown and too much margin tends to limit the performance of critical circuits.

NEC’s newly-developed device/circuit-design technology has successfully solved this issue as it predicts the random variations within individual devices and the impact of those variations on circuit performance by very large-scale statistical circuit simulation. The new variation-aware design technology has great potential for reducing time to market, from LSI design to mass fabrication, while ensuring high reliability and low cost by avoiding the redesign of circuits.

This research breakthrough has provided NEC and NEC Electronics with a strong direction for future technological progress and system-LSI development, and both companies will continue to carry out aggressive research and development in this field toward the realization of next generation low-cost, low-power, and high-speed system LSIs.

NEC and NEC Electronics will continue to carry out research, which takes into consideration the emergence of new variation effects and mitigation technologies in the future, in cooperation with the “MIRAI”*4 project in Japan .

The results of this research were announced at the VLSI symposium, which is being held in Kyoto, Japan, from June 12 -14, 2007.

*Notes:

(1) Intrinsic fluctuation:
As the structural dimension of devices approaches the sub-micron level, the number and position of impurity atoms differ for individual devices. In addition, device characteristics become sensitive to microscopic structural fluctuations, such as the roughness of the line edge of gate electrodes. These variations are statistically random and considered “intrinsic” characteristics of deeply scaled devices, in contrast to variations resulting during fabrication, such as thermal process temperature and time fluctuations for each wafer process.

(2) Atomistic process/Device simulations:
NEC and NEC Electronics have developed computer simulations that are capable of calculating the three-dimensional positions of every impurity atom in the silicon crystal. These simulations can predict device characteristics for multiple devices as necessary by considering the intrinsic random fluctuations in accordance with specific fabrication processes.

(3) Compact statistical model for very large-scale circuit simulation
Very large-scale circuit simulation is carried out through the modeling of transistor currents by mathematical approximation, using the complicated analytical function of input voltages. Until recently, it was believed that the formula for the complicated analytical approximation model was not capable of expressing the realistic/practical variations of individual device characteristics, especially before the establishment of new device architecture and the development of mass fabrication capability.

(4) MIRAI: Millennium Research for Advanced Information Technology
http://www.miraipj.jp/en/